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general description the ds1086l econoscillator is a 3.3v programmable clock generator that produces a spread-spectrum (dithered) square-wave output of frequencies from 130khz to 66.6mhz. the selectable dithered output reduces radiated-emission peaks by dithering the fre- quency 0.5%,1%, 2%, 4%, or 8% below the pro- grammed frequency. the ds1086l has a power-down mode and an output-enable control for power-sensitive applications. all the device settings are stored in non- volatile (nv) eeprom memory allowing it to operate in stand-alone applications. applications printers copiers pcs computer peripherals cell phones cable modems features ? user-programmable square-wave generator ? frequencies programmable from 130khz to 66.6mhz ? 0.5%, 1%, 2%, 4%, or 8% selectable dithered output ? adjustable dither rate ? glitchless output-enable control ? 2-wire serial interface ? nonvolatile settings ? 2.7v to 3.6v supply ? no external timing components required ? power-down mode ? 5khz master frequency step size ? emi reduction ? industrial temperature range: -40? to +85? ds1086l 3.3v spread-spectrum econoscillator pdn oe gnd 1 2 8 7 scl sda sprd v cc out sop top view 3 4 6 5 ds1086l pin configuration ordering information xtl1/osc1 p xtl2/osc2 dithered 130khz to 66.6mhz output decoupling capacitors (0.1 f and 0.01 f) *sda and scl can be connected directly high if the ds1086l never needs to be programmed in-circuit, including during production testing. sprd out v cc v cc v cc gnd n.c. scl* sda* pdn oe ds1086l typical operating circuit rev 1; 9/07 part temp range pin-package DS1086LU -40? to +85? 8 sop (118 mil) econoscillator is a trademark of dallas semiconductor. ________________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
ds1086l 3.3v spread-spectrum econoscillator 2 _______________________________________________________________________________________ absolute maximum ratings recommended dc operating conditions (v cc = 2.7v to 3.6v, t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.7 3.3 3.6 v high-level input voltage (sda, scl, sprd, pdn , oe) v ih 0.7 x v cc v cc + 0.3 v low-level input voltage (sda, scl sprd, pdn , oe) v il -0.3 0.3 x v cc v dc electrical characteristics (v cc = 2.7v to 3.6v, t a = -40? to +85?.) parameter symbol conditions min typ max units high-level output voltage (out) v oh i oh = -4ma, v cc = min 2.4 v low-level output voltage (out) v ol i ol = 4ma 0 0.4 v v ol1 3ma sink current 0 0.4 low-level output voltage (sda) v ol2 6ma sink current 0 0.6 v high-level input current i ih v cc = 3.6v 1 a low-level input current i il v il = 0 -1 a supply current (active) i cc c l = 15pf (output at default frequency) 10 ma standby current (power-down) i ccq power-down mode 10 ? voltage range on v cc relative to ground ..........-0.5v to +6.0v voltage range on sprd, pdn , oe, sda, and scl relative to ground* ..................................-0.5 to (v cc + 0.5v) operating temperature range ...........................-40? to +85? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature ..................see ipc/jedec j-std-020a * this voltage must not exceed 6.0v.
ds1086l 3.3v spread-spectrum econoscillator _______________________________________________________________________________________ 3 master oscillator characteristics (v cc = 2.7v to 3.6v, t a = -40? to +85?.) parameter symbol conditions min typ max units master oscillator frequency f osc (note 2) 33.3 66.6 mhz default master oscillator frequency f 0 factory-programmed default 48.65 mhz default frequency (f 0 ) -0.5 +0.5 master oscillator frequency tolerance f 0 f 0 v cc = 3.3v, t a = +25 c (notes 3,17) dac step size -0.5 +0.5 % default frequency -0.75 +0.75 voltage frequency variation f v f 0 over voltage range, t a = +25 c (note 4) dac step size -0.75 +0.75 % default frequency -2.0 +0.75 66.6mhz -2.0 +0.75 temperature frequency variation f t f 0 over temperature range, v cc = 3.3v (note 5) 33.3mhz -2.5 +0.75 % prescaler bits js2, js1, js0 = 000 0.5 prescaler bits js2, js1, js0 = 001 1 prescaler bits js2, js1, js0 = 010 2 prescaler bits js2, js1, js0 = 100 4 dither frequency range (note 6) f f 0 prescaler bits js2, js1, js0 = 111 8 % integral nonlinearity of frequency inl entire range (note 7) -0.6 +0.3 % dac step size between two consecutive dac values (note 8) 5 khz dac span frequency range for one offset setting (table 2) 5.12 mhz dac default factory default register setting 500 decimal offset step size between two consecutive offset values (table 2) 2.56 mhz offset default os factory default offset register setting (5 lsbs) (table 2) range (5 lsbs of range register) hex prescaler bits js4, js3 = 00 f 0 /8192 prescaler bits js4, js3 = 01 f 0 /4096 dither rate prescaler bits js4, js3 = 10 f 0 /2048 hz
ds1086l 3.3v spread-spectrum econoscillator 4 _______________________________________________________________________________________ ac electrical characteristics (v cc = 2.7v to 3.6v, t a = -40? to +85?.) parameter symbol conditions min typ max units frequency stable after prescaler change 1 period frequency stable after dac or offset change t dacstab (note 9) 0.1 1 ms power-up time t p or + t stab (note 10) 0.1 0.5 ms enable of out after exiting power-down mode t stab (note 18) 200 ? out high-z after entering power-down mode t pdn 100 ? load capacitance c l (note 11) 15 50 pf output duty cycle (out) default frequency 45 55 % rise and fall time (oe, pdn ) 1s ac electrical characteristics?-wire interface (v cc = 2.7v to 3.6v, t a = -40? to +85?.) parameter symbol conditions min typ max units fast mode 400 scl clock frequency f scl standard mode (note 12) 100 khz fast mode 1.3 bus free time between a stop and start condition t buf standard mode (note 12) 4.7 ? fast mode 0.6 hold time (repeated) start condition t hd:sta standard mode (notes 12, 13) 4.0 ? fast mode 1.3 low period of scl t low standard mode (note 12) 4.7 ? fast mode 0.6 high period of scl t high standard mode (note 12) 4.0 ? fast mode 0.6 setup time for a repeated start t su:sta standard mode (note 12) 4.7 ? fast mode data hold time t hd:dat standard mode (notes 12, 14, 15) 0 0.9 ? fast mode 100 data setup time t su:dat standard mode (note 12) 250 ns fast mode 20 + 0.1c b 300 rise time of both sda and scl signals t r standard mode (note 16) 20 + 0.1c b 1000 ns fast mode 20 + 0.1c b 300 fall time of both sda and scl signals t f standard mode (note 16) 20 + 0.1c b 1000 ns
ds1086l 3.3v spread-spectrum econoscillator _______________________________________________________________________________________ 5 ac electrical characteristics?-wire interface (continued) (v cc = 2.7v to 3.6v, t a = -40? to +85?.) parameter symbol conditions min typ max units fast mode 0.6 setup time for stop t su:sto standard mode 4.0 ? capacitive load for each bus line c b (note 16) 400 pf eeprom write cycle time t wr 10 ms input capacitance c i 5pf nonvolatile memory characteristics (v cc = 2.7v to 3.6v) parameter symbol conditions min typ max units eeprom writes +70? 10,000 note 1: all voltages are referenced to ground. note 2: dac and offset register settings must be configured to maintain the master oscillator frequency within this range. correct operation of the device is not guaranteed if these limits are exceeded. note 3: this is the absolute accuracy of the master oscillator frequency at the default settings. note 4: this is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at t a = +25?. note 5: this is the percentage frequency change from the +25? frequency due to temperature at v cc = 3.3v. the maximum temper- ature change varies with the master oscillator frequency setting. the minimum occurs at the default master oscillator frequen- cy (f default ). the maximum occurs at the extremes of the master oscillator frequency range (33.3mhz or 66.6mhz). note 6: the dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency. note 7: the integral nonlinearity of the frequency is a measure of the deviation from a straight line drawn between the two end- points (f osc(min) to f osc(max) ) of the range. the error is in percentage of the span. note 8: this is true when the prescaler = 1. note 9: frequency settles faster for small changes in value. during a change, the frequency transitions smoothly from the original value to the new value. note 10: this indicates the time elapsed between power-up and the output becoming active. an on-chip delay is intentionally introduced to allow the oscillator to stabilize. t stab is equivalent to approximately 512 master clock cycles and therefore depends on the programmed clock frequency. note 11: output voltage swings can be impaired at high frequencies combined with high output loading. note 12: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat > 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line at least t r max + t su:dat = 1000ns + 250ns = 1250ns before the scl line is released. note 13: after this period, the first clock pulse is generated. note 14: a device must internally provide a hold time of at least 300ns for the sda signal (referred to as the v ih min of the scl signal) to bridge the undefined region of the falling edge of scl. note 15: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 16: c b ?otal capacitance of one bus line, timing referenced to 0.9 x v cc and 0.1 x v cc . note 17: typical frequency shift due to aging is ?.5%. aging stressing includes level 1 moisture reflow preconditioning (24hr +125? bake, 168hr 85?/85%rh moisture soak, and three solder reflow passes +240 +0/-5? peak) followed by 1000hr max v cc biased 125? htol, 1000 temperature cycles at -55? to +125?, 96hr 130?/85%rh/3.6v hast and 168hr 121?/2 atm steam/unbiased autoclave. note 18: t stab is the time required after exiting power-down to the beginning of output oscillations. in addition, a delay of t dacstab is required before the frequency will be within its specified tolerance.
typical operating characteristics (v cc = 3.3v, t a = 25?, unless otherwise noted.) ds1086l 3.3v spread-spectrum econoscillator 6 _______________________________________________________________________________________ supply current vs. master oscillator frequency ds1086l toc01 master frequency (mhz) supply current (ma) 63 60 36 39 42 48 51 54 45 57 2 3 4 5 6 7 8 9 1 33 66 15pf load 4.7pf load prescaler = 1 supply current vs. temperature ds1086l toc02 temperature ( c) supply current (ma) 60 35 10 -15 4 5 6 7 8 9 10 3 -40 85 f o = 66mhz f o = 50mhz f o = 33.3mhz prescaler = 1 15pf load supply current vs. prescaler ds1086l toc03 prescaler supply current ( m a) 100 10 1 2 3 4 5 6 7 0 1 1000 f o = 50mhz 15pf load master oscillator frequency percent change vs. supply voltage ds1086l toc04 supply voltage (v) percent changet (%) 3.3 3.0 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 2.7 3.6 f o = 66mhz f o = 50mhz f o = 33.3mhz prescaler = 1 master oscillator frequency percent change vs. temperature ds1086l toc05 temperature ( c) percent change (%) 60 35 -15 10 -1.25 -1.00 -0.75 -0.50 0 -0.25 0.25 0.50 -1.50 -40 85 f o = 66mhz f o = 50mhz f o = 33.3mhz prescaler = 1 15pf load duty cycle vs. temperature ds1086l toc06 temperature ( c) duty cycle (%) 60 35 10 -15 51 52 53 54 55 50 -40 85 f o = 66mhz f o = 50mhz f o = 33.3mhz prescaler = 1 duty cycle vs. supply voltage supply voltage (v) 3.3 3.0 2.7 3.6 ds1086l toc07 duty cycle (%) 51 52 53 54 55 f o = 66mhz f o = 50mhz f o = 33.3mhz prescaler = 1
ds1086l 3.3v spread-spectrum econoscillator power-down current vs. temperature ds1086l toc09 temperature ( c) power-down current ( a) 60 35 10 -15 1.46 1.48 1.50 1.52 1.54 1.56 1.58 1.60 1.62 1.64 1.44 -40 85 supply current with output disabled vs. supply voltage ds1086l toc10 supply voltage (v) supply current (ma) 3.3 3.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 2.7 3.6 f o = 66mhz supply current with output disabled vs. temperature ds1086l toc11 supply voltage (v) supply current (ma) 60 35 10 -15 2.3 2.4 2.5 2.6 2.7 2.2 -40 85 f o = 66mhz typical operating characteristics (continued) (v cc = 3.3v, t a = 25?, unless otherwise noted.) _______________________________________________________________________________________ 7 power-down current vs. supply voltage ds1086l toc08 supply voltage (v) power-down current ( a) 3.0 3.3 1.1 1.2 1.3 1.4 1.6 1.5 1.7 1.8 1.0 2.7 3.6
ds1086l 3.3v spread-spectrum econoscillator 8 _______________________________________________________________________________________ pin description pin name function 1 out oscillator output. the output frequency is determined by the offset, dac, and prescaler registers. 2 sprd dither enable. when the pin is high, the dither is enabled. when the pin is low, the dither is disabled. 3v cc power supply 4 gnd ground 5oe output enable. when the pin is high, the output buffer is enabled. when the pin is low, the output is disabled but the master oscillator is still on. 6 pdn power-down. when the pin is high, the master oscillator is enabled. when the pin is low, the master oscillator is disabled (power-down mode). 7 sda 2-wire serial data. this pin is for serial data transfer to and from the device. the pin is open drain and can be wire-ored with other open-drain or open-collector interfaces. 8 scl 2-wire serial clock. this pin is used to clock data into the device on rising edges and clock data out on falling edges. dithered 260khz to 133mhz output decoupling capacitors (0.1 f and 0.01 f) sprd out v cc v cc v cc 4.7k 4.7k v cc 2-wire interface gnd scl sda pdn oe ds1086l processor-controlled mode xtl1/osc1 p xtl2/osc2 dithered 130khz to 66.6mhz output decoupling capacitors (0.1 f and 0.01 f) *sda and scl can be connected directly high if the ds1086l never needs to be programmed in-circuit, including during production testing. sprd out v cc v cc v cc gnd n.c. scl* sda* pdn oe ds1086l stand-alone mode spectrum comparison (12okhz bw, sample detect) ds1086l fig01 frequency (mhz) power spectrum (dbm) 51 49 47 45 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 43 53 0.5% no spread fo = 50mhz dither rate = fo/4096 2% 8% figure 1. clock spectrum dither comparison maximum thermal variation vs. master oscillator frequency ds1086l fig02 master frequency (mhz) supply current (ma) 63 60 36 39 42 48 51 54 45 57 -4% -3% -2% -1% 0 1% 2% 3% -5% 33 66 figure 2. temperature variation over frequency
ds1086l 3.3v spread-spectrum econoscillator _______________________________________________________________________________________ 9 detailed description a block diagram of the ds1086l is shown in figure 3. the internal master oscillator generates a square wave with a 33.3mhz to 66.6mhz frequency range. the fre- quency of the master oscillator can be programmed with the dac register over a two-to-one range in 5khz steps. the master oscillator range is larger than the range possible with the dac step size, so the offset register is used to select a smaller range of frequencies over which the dac spans. the prescaler can then be set to divide the master oscillator frequency by 2 x (where x equals 0 to 8) before routing the signal to the output (out) pin. a programmable triangle-wave generator injects an off- set element into the master oscillator to dither its output 0.5%, 1%, 2%, 4%, or 8%. the dither magnitude is con- trolled by the js2, js1, and js0 bits in the prescaler word and enabled with the sprd pin. futhermore, the dither rate is controlled by the js4 and js3 bits in the prescaler word and determines the frequency of the dither. the maximum spectral attenuation occurs when the prescaler is set to 1 and is reduced by 2.7db for every factor of 2 that is used in the prescaler. this hap- pens because the prescaler? divider function tends to average the dither in creating the lower frequency. however, the most stringent spectral emission limits are imposed on the higher frequencies where the prescaler is set to a low divider ratio. the external control input, oe, gates the clock output buffer. the pdn pin disables the master oscillator and turns off the clock output for power-sensitive applica- tions*. on power-up, the clock output is disabled until power is stable and the master oscillator has generated 512 clock cycles. both controls feature a synchronous enable that ensures there are no output glitches when the output is enabled. the control registers are programmed through a 2-wire interface and are used to determine the output frequen- cy and settings. once programmed into eeprom, since the register settings are nv, the settings only need to be reprogrammed if it is desired to reconfigure the device. sda v cc scl 2-wire interface v cc dac offset eeprom control registers prescaler addr range sprd pdn out oe dac triangle wave generator voltage-controlled oscillator prescaler by 1, 2, 4...256 gnd master oscillator output dither signal dither control frequency control voltage ds1086l figure 3. block diagram * the power-down command must persist for at least two out- put frequency cycles plus 10? for deglitching purposes.
ds1086l 3.3v spread-spectrum econoscillator 10 ______________________________________________________________________________________ the output frequency is determined by the following equation: where: min frequency of selected offset range is the lowest frequency (shown in table 2 for the correspond- ing offset). dac value is the value of the dac register (0 to 1023). prescaler is the value of 2 x where x = 0 to 8. see the example frequency calculations section for a more in-depth look at using the registers. ________________register definitions the ds1086l registers are used to program the output frequency, dither percent, dither rate, and 2-wire address. table 1 shows a summary of the registers and detailed descriptions follow below. prescaler (02h) the prescaler word is a two-byte value containing control bits for the prescaler (p3 to p0), output control (lo/ hiz ), the jitter rate (js4 to js3), as well as control bits for the jitter percentage (js2 to js0). the prescaler word is read and written using two-byte reads and writes beginning at address 02h. js4 to js3: jitter rate . this is the frequency of the tri- angle wave generator and the modulation frequency that the output is dithered. it can be programmed to the master oscillator frequency, f osc , divided by either 8192, 4096, or 2048. js4 js3 jitter rate 00 f osc /8192 01 f osc /4096 (default) 10 f osc /2048 f output min frequency of selected offset range dac value khz step size prescaler ( ) ( ) = + 5 offset frequency range (mhz) os - 6 30.74 to 35.86 os - 5 33.30 to 38.42 os - 4 35.86 to 40.98 os - 3 38.42 to 43.54 os - 2 40.98 to 46.10 os - 1 43.54 to 48.66 os* 46.10 to 51.22 os + 1 48.66 to 53.78 os + 2 51.22 to 56.34 os + 3 53.78 to 58.90 os + 4 56.34 to 61.46 os + 5 58.90 to 64.02 os + 6 61.46 to 66.58 * factory default setting. os is the integer value of the five lsbs of the range register. register addr msb binary lsb factory default access prescaler 02h js4 js3 js2 js1 js0 lo/ hiz p3 p2 0 1 1 0 0 0 0 0 r/w prescaler p1 p0 x x x x x x x x x x x x 0 0 x x x x x r/w dac (msb) 08h b9 b8 b7 b6 b5 b4 b3 b2 01111101b r/w dac (lsb) b1 b0 x 0 x 0 x 0 x 0 x 0 x 0 00000000b r/w offset 0eh x 1 x 1 x 1 b4 b3 b2 b1 b0 1 1 1 - - - - - b r/w addr 0dh x 1 x 1 x 1 x 1 wc a2 a1 a0 11110000b r/w range 37h x x x x x x b4 b3 b2 b1 b0 x x x - - - - - b r write ee 3fh no data table 1. register summary x 0 = don? care, reads as zero. x 1 = don? care, reads as one. x x = don? care, reads indeterminate. x = don? care. table 2. offset settings
ds1086l 3.3v spread-spectrum econoscillator ______________________________________________________________________________________ 11 js2 to js0: jitter percentage . these three bits select the amount of jitter in percent. the sprd pin must be a logic high for the jitter to be enabled. bit combinations not shown are reserved. lo/ hiz : output low or high-z. this bit determines the state of the output pin when the device is in power- down mode or when the output is disabled. if lo/ hiz = 0, the output is hiz when in power-down or disabled. if lo/ hiz = 1, the output is held low when in power-down or disabled. p3 to p0: prescaler divider. these bits divide the master oscillator frequency by 2 x , where x is p3 to p0 and can be from 0 to 8. any prescaler value entered greater than 8 decodes as 8. dac (08h) b9 to b0: dac setting. the dac word sets the master oscillator frequency to a specific value within the cur- rent offset range. each step of the dac changes the master oscillator frequency by 5khz. the dac word is read and written using two-byte reads and writes beginning at address 08h. offset (0eh) b4 to b0: offset. this value selects the master oscilla- tor frequency range that can be generated by varying the dac word. valid frequency ranges are shown in table 2. correct operation of the device is not guaran- teed for values of offset not shown in the table. the default offset value (os) is factory trimmed and can vary from device to device. therefore, to change frequency range, os must be read so the new offset value can be calculated relative to the default. for example, to generate a master oscillator frequency within the largest range (61.4mhz to 66.6mhz), table 2 indicates that the offset must be programmed to os + 6. this is done by reading the range register and adding 6 to the value of bits b4 to b0. the result is then written into bits b4 to b0 of the offset register. additional examples are provided in the example frequency calculations section. range (37h) b4 to b0: range: this read-only, factory programmed value is a copy of the factory default offset (os). os is required to program new master oscillator frequencies shown in table 2. the read-only backup is important because the offset register is eeprom and is likely to be overwritten. addr (0dh) wc: eeprom write control bit. the wc bit enables/disables the automatic writing of registers to eeprom. this prevents eeprom wear out and elimi- nates the eeprom write cycle time. if wc = 0 (default), register writes are automatically written to eeprom. if wc = 1, register writes are stored in sram and only written into eeprom when the user sends a write ee command. if power is cycled to the device, then the last value stored in eeprom is recalled. wc = 1 is ideal for applications that frequently modify the fre- quency/registers. regardless of the value of the wc bit, the value of the addr register is always written immediately to eeprom. a2 to a0: device address bits. these bits determine the 2-wire slave address of the device. they allow up to eight devices to be attached to the same 2-wire bus and to be addressed individually. write ee command (3fh) this command can be used when wc = 1 (see the wc bit in addr register) to transfer all registers from sram into eeprom. the time required to store the values is one eeprom write cycle time. this command is not needed if wc = 0. js2 js1 js0 jitter % 0 0 0 0.5 0 0 1 1 0 1 0 2 1 0 0 4 1 1 1 8
ds1086l 3.3v spread-spectrum econoscillator 12 ______________________________________________________________________________________ example frequency calculations example #1: calculate the register values needed to generate a desired output frequency of 11.0592mhz. since the desired frequency is not within the valid mas- ter oscillator range of 33.3mhz to 66.6mhz, the prescaler must be used. valid prescaler values are 2 x where x equals 0 to 8 (and x is the value that is pro- grammed into the p3 to p0 bits of the prescaler reg- ister). equation 1 shows the relationship between the desired frequency, the master oscillator frequency, and the prescaler. by trial and error, x is incremented from 0 to 8 in equation 2, finding values of x that yield master oscillator frequencies within the range of 33.3mhz to 66.6mhz. equation 2 shows that a prescaler of 4 (x = 2) and a master oscillator frequency of 44.2368mhz generates our desired frequency. writing 0080h to the prescaler register sets the prescaler to 4. be aware that other settings also reside in the prescaler register. f master oscillator = f desired x prescaler = f desired x 2 x f master oscillator = 11.0592mhz x 2 2 = 44.2368mhz once the target master oscillator frequency has been calculated, the value of offset can be determined. using table 2, 44.2368mhz falls within both os - 1 and os - 2. however, choosing os - 1 would be a poor choice since 44.2368mhz is so close to os - 1? mini- mum frequency. on the other hand, os - 2 is ideal since 44.2368mhz is close to the center of os - 2? frequency span. before the offset register can be programmed, the default value of offset (os) must be read from the range register (last five bits). in this example, 12h (18 decimal) was read from the range register. os - 2 for this case is 10h (16 deci- mal). this is the value that is written to the offset reg- ister. finally, the two-byte dac value needs to be deter- mined. since os - 2 only sets the range of frequencies, the dac selects one frequency within that range as shown in equation 3. f master oscillator = (min frequency of selected offset range) + (dac value x 5khz) valid values of dac are 0 to 1023 (decimal) and 5khz is the step size. equation 4 is derived from rearranging equation 3 and solving for the dac value. since the two-byte dac register is left justified, 647 is converted to hex (0287h) and bit-wise shifted left six places. the value to be programmed into the dac reg- ister is a1c0h. in summary, the ds1086l is programmed as follows: prescaler = 0080h offset = os - 2 or 10h (if range was read as 12h) dac = a1c0h notice that the dac value was rounded. unfortunately, this means that some error is introduced. to calculate how much error, a combination of equation 1 and equation 3 is used to calculate the expected output fre- quency. see equation 5. f min frequency of selected offset range dac value x khz step size prescaler f mhz x khz mhz mhz output output ( ) ( ) (. ) ( ) . . = + = + = = 5 41 0 647 5 4 44 235 4 11 05875 dac value f min frequency of selected offset range khz step size dac value mhz mhz khz step size decimal master oscillator ( ) (. . ) . ( ) = ? = ? = 5 44 2368 41 0 5 647 36 647 f f prescaler f desired master oscillator master oscillator x = = 2 (1) (4) (2) (3) (5)
ds1086l 3.3v spread-spectrum econoscillator ______________________________________________________________________________________ 13 the expected output frequency is not exactly equal to the desired frequency of 11.0592mhz. the difference is 450hz. in terms of percentage, equation 6 shows that the expected error is 0.004%. the expected error assumes typical values and does not include deviations from the typical as specified in the electrical tables. example #2: calculate the register values needed to generate a desired output frequency of 50mhz. since the desired frequency is already within the valid master oscillator frequency range, the prescaler is set to divide by 1, and hence, prescaler = 0000h (currently ignoring the other setting). f master oscillator = 50.0mhz x 2 0 = 50.0mhz next, looking at table 2, os + 1 provides a range of frequencies centered around the desired frequency. to determine what value to write to the offset register, the range register must first be read. assuming 12h was read in this example, 13h (os + 1) is written to the offset register. finally, the dac value is calculated as shown in equation 8. the result is then converted to hex (0118h) and then left-shifted, resulting in 4600h to be programmed into the dac register. in summary, the ds1086l is programmed as follows: prescaler = 0000h offset = os + 1 or 13h (if range was read as 12h) dac = 4600h since the expected output frequency is equal to the desired frequency, the calculated error is 0%. f mhz khz mhz mhz output (. ) ( ) . . = + = = 48 6 280 5 2 50 0 1 50 0 0 dac value mhz mhz khz step size decimal (. . ) . ( ) = ? = 50 0 48 6 5 280 00 % % . . . . .% error ff f error mhz mhz mhz hz mhz expected desired expected desired expected = ? = ? == 100 11 0592 11 05875 11 0592 100 450 11 0592 100 0 004 stop condition or repeated start condition repeated if more bytes are transferred ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 4. 2-wire data transfer protocol (6) (7) (8) (9)
ds1086l 14 ______________________________________________________________________________________ _______2-wire serial port operation 2-wire serial data bus the ds1086l communicates through a 2-wire serial interface. a device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. the device that controls the message is called a ?aster.?the devices that are controlled by the master are ?laves.?a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions must con- trol the bus. the ds1086l operates as a slave on the 2- wire bus. connections to the bus are made through the open-drain i/o lines sda and scl. the following bus protocol has been defined (see figures 4 and 6): data transfer can be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is sta- ble for the duration of the high period of the clock sig- nal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop con- sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 6. 2-wire ac characteristics msb device identifier device address read/write bit 1 0 1 1 a2 a1 a0 r/w lsb figure 5. slave address 3.3v spread-spectrum econoscillator
ds1086l 3.3v spread-spectrum econoscillator ______________________________________________________________________________________ 15 ditions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications a standard mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. the ds1086l works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. when the ds1086l eeprom is being written to, it is not able to perform additional responses. in this case, the slave ds1086l sends a not acknowledge to any data transfer request made by the master. it resumes normal operation when the eeprom operation is com- plete. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figures 4, 5, 6, and 7 detail how data transfer is accomplished on the 2-wire bus. depending upon the state of the r/ w bit, two types of data transfer are pos- sible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2) data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge is returned. the master device generates all the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. the ds1086l can operate in the following two modes: slave receiver mode: serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is per- formed by hardware after reception of the slave address and direction bit. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer direc- tion is reversed. serial data is transmitted on sda by the ds1086l while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. slave address figure 5 shows the first byte sent to the device. it includes the device identifier, device address, and the r/ w bit. the device address is determined by the addr register. registers/commands see table 1 for the complete list of registers/com- mands and figure 7 for an example of using them. __________applications information power-supply decoupling to achieve the best results when using the ds1086l, decouple the power supply with 0.01? and 0.1? high-quality, ceramic, surface-mount capacitors. surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. these capacitors should be placed as close to pins 3 and 4 as possible. stand-alone mode scl and sda cannot be left floating when they are not used. if the ds1086l never needs to be programmed in-circuit, including during production testing, sda and scl can be tied high. the sprd pin must be tied either high or low.
ds1086l 3.3v spread-spectrum econoscillator chip topology transistor count: 9052 substrate connected to ground package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . slave ack 10 1 1 r/w a0* a1* slave ack a2* msb lsb device identifier device address read/ write msb lsb command/register address slave ack msb lsb b7 b6 b5 b4 b3 b2 b1 b0 slave ack stop *the address determined by a0, a1, and a2 must match the address set in the addr register. data typical 2-wire write transaction example 2-wire transactions (when a0, a1, and a2 are zero) a) single byte write -write offset register b) single byte read -read offset register c) two byte write -write dac register d) two byte read -read dac register start start start start start b0h b0h b0h b0h slave ack slave ack slave ack slave ack 0eh 0eh 08h 08h slave ack slave ack slave ack slave ack data slave ack stop offset 10110000 10110000 10110000 10110000 10110001 repeated start slave ack dac msb master ack dac lsb data master nack stop data b1h b7 b6 b5 b4 b3 b2 b1 b0 00001110 00001110 00001000 00001000 repeated start data offset master nack stop slave ack 10110001 b1h stop slave ack dac lsb data slave ack dac msb data figure 7. 2-wire transactions maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history pages changed at rev 1: 10

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